SystemVerilog Queue Queue is a variable size, ordered collection of homogeneous elements which can grow and shrink. The entire group can be referenced as a whole, or the individual data type can be referenced by name. To subscribe to this RSS feed, copy and paste this URL into your RSS reader. Unpacked Structure of type 'lp_s' can't be assigned by multiple Means it describe the structure and behavior of electronic circuits as well as it verifies the electronic circuits written in a Hardware Description Language. Functions declared inside structs are not supported as of IEEE Std 1800-2012. However, SystemVerilog queue comes with a useful and flexible function called sort (). In the below example, byte, enum and bit types are grouped in the struct. a ' before concatenation operator to convert it to a valid Asking for help, clarification, or responding to other answers. With Queue we can insert or delete any element without the performance hit as with dynamic array that has to allocate a new array and copy the entire content. Note, you can't use default:0 here because 0 is not a valid value type to assign to an enum. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. It supports various datatypes like enum, union, struct, string, class. Hi, I’m trying to use struct as data type in queues. A Queue is analogous to one dimensional unpacked array that grows and shrinks automatically. Classes can use virtual interfaces, with the actual interface passed to the constructors. Queue is introduced in SystemVerilog. It covers a wide variety of topics such as understanding the basics of DDR4, SytemVerilog language constructs, UVM, Formal Verification, Signal Integrity and Physical Design. The order could be as simple as find any first vacant entry or find a next vacant entry from previous allocation or find the last entry that became available recently. SystemVerilog adds C-like structures to Verilog. A "struct" in 'e' is equivalent to "class" [Dynamic] in SV. Struct Syntax. SystemVerilog introduces new data types with the following benefits. SystemVerilog wurde von Accellera entwickelt und ist eine Erweiterung des IEEE 1364–2001 Verilog HDL. But I'm not understanding something here. Hi all, I try using a queue of classes but there seems to be a problem when trying to read an item from the queue. Is it even possible? A SystemVerilog-Python connection, therefore, needs to follow certain guidelines, otherwise, the communication will fail. Here is a snippet of a statement within an always block to be executed when "reset" is asserted: foreach (iS_CONTROL_REGISTERS_d1[N]) 4 comments on “ System Verilog : Queues ” Ramya October 27, 2014 at 7:05 pm. With Queue we can insert or delete any element without the performance hit as with dynamic array that has to allocate a new array and copy the entire content. I think this should solve the issue. They can also be manipulated by indexing, concatenation and … Queue is introduced in SystemVerilog. Queue is a variable size, ordered collection of homogeneous elements which can grow and shrink. A structure is unpacked by default and can be defined using the struct keyword and a list of member declarations can be provided within the curly brackets followed by the name of the structure. rev 2021.1.18.38333, Stack Overflow works best with JavaScript enabled, Where developers & technologists share private knowledge with coworkers, Programming & related technical career opportunities, Recruit tech talent & build your employer brand, Reach developers & technologists worldwide, Initializing queue of structures using replication in System verilog, Difference between structure and union in System verilog, concatenation of arrays in system verilog, Initializing a 4bit input in system verilog, I'm not seeing 'tightly coupled code' as one of the drawbacks of a monolithic application architecture. Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. This does the trick, and the notes and errors go away. Struct is defined with the Struct keyword followed by variables of multiple data type with in the curly braces. To learn more, see our tips on writing great answers. Looking over the syntax for structure declaration, a struct_union_member is a data_type_or_void and a function is not data_type. It covers a wide variety of topics such as understanding the basics of DDR4, SytemVerilog language constructs, UVM, Formal Verification, Signal Integrity and Physical Design. SystemVerilog is based on Verilog, VHDL and c++ programming language. Pack bytes into an int; 1.1 Byte variables to an int; 1.2 Array of bytes to an int ; 2. Why is it so hard to build crewed rockets/spacecraft able to reach escape velocity? typedef struct packed { logic [17-1:0] instr; logic [10-1:0] addr; The article’s sections are: Introduction; 1. The class-based driver must drive the module-based DUT through a virtual interface that drives a real interface. Is it even possible? SystemVerilog Arrays, Flexible and Synthesizable, SystemVerilog arrays can be either packed or unpacked. flanter over 11 years ago. SystemVerilog offers many improved data structures compared with Verilog. my_data_struct.a = 123; typedef struct packed { type_1 var_1; type_2 … In the article, Queues In SystemVerilog, we will discuss the topics of SystemVerilog queues. It is based on classes. I'm getting strange behavior. SystemVerilog extends Verilog by introducing C like data types. `include "my_struct_s.v" Defining the struct. This doesn't work right with Vivado, and I'm not sure why. SystemVerilog . so there wont be much need to randomize queue. Can someone shed light on what this SystemVerilog code should do: typedef struct { logic [15:0] a; logic [15:0] b; logic [15:0] c; } my_struct; localparam my_struct s = '{default:'1, c:0}; Is this legal? Making statements based on opinion; back them up with references or personal experience. Only members of struct which are declared as rand or randc are only randomized. SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. January 17, 2017 April 28, 2017 by Jason Yu April 28, 2017 by Jason Yu SystemVerilog queue of classes. your coworkers to find and share information. SNUG Silicon Valley 2013 3 Synthesizing SystemVerilog 1.0 Introduction — debunking the Verilog vs. SystemVerilog myth There is a common misconception that “Verilog” is a hardware modeling language that is synthesizable, and “SystemVerilog” is a verification language that is not synthesizable.That is completely false! One class classifier vs binary classifier. Yes, it is legal SystemVerilog. This video covers the main 6 data types for a quick revision ! Queues are used in Digital design when the Data from a Stream is needed to be stored into a Structure, manipulated and taken out of Order based on a protocol or events in the Design. SystemVerilog; Verification ; Constructs ; Interface ; OOPS ; Randomization ... QUEUES A queue is a variable-size, ordered collection of homogeneous elements. SystemVerilog Queue. flanter over 11 years ago. Viewed 633 times 1. Thanks for contributing an answer to Stack Overflow! The SystemVerilog struct has to be re-defined in C. Byte and int are directly compatible with C, while the packed array is redefined using the macro SV_BIT_PACKED_ARRAY(width, name). Join Stack Overflow to learn, share knowledge, and build your career. For reverse sorting there is a similar function called rsort (): 1. Refer to IEEE Std 1800-2012 § 10.9 Assignment patterns. Hi all, I try using a queue of classes but there seems to be a problem when trying to read an item from the queue. queues. I can't quite figure out the spec well enough to tell. randc is not allowed on unpacked structs. Randomization is very key to CRT for the creation of tests targeted toward a coverage-driven verification methodology where the testplan is more focused on the coverage rather than directed tests. We use cookies to ensure that we give you the best experience on our website. size of the target. Full Access. A SystemVerilog queue is a First In First Out scheme which can have a variable size to store elements of the same data type. Add Part-VII. The proposed project will create an IEEE standard that is leveraged from Accellera SystemVerilog 3.1a. What happens to a photon when it loses all its energy? Stack Overflow for Teams is a private, secure spot for you and SystemVerilog’s data type system allows you to define quite complex types. A systemverilog implementation of the data structures: priority queue, queue and stack. Which Diffie-Hellman Groups does TLS 1.3 support? Active 1 year, 8 months ago. I tried out below ways without success. I define a struct which stores the data elements of an item in the queue as follows: typedef struct {bit[31:0] addr, bit[3:0] id, bit[63:0] data; bit flag} packet_t; packet_t q1 [$]; I want to populate the addr everytime a new addr comes in, like: randomize queue size In below example, queue size will get randomized based on size constraint, and queue elements will get random values Declare queue with rand On randomization … Continue reading "SystemVerilog Queue Randomization" The SystemVerilog struct groups the data types of multiple types. system-verilog According to 1800-2012 specs, Queue::delete( [input int index] ) deletes an element of a queue in SystemVerilog, furthermore, a Queue can perform the same operations as an unpacked Array, giving it access to: Array::find_first_index( ) which returns the index of the first element matching a certain criteria. How to describe a cloak touching the ground behind you as you walk? systemverilog.io is a resource that explains concepts related to ASIC, FPGA and system design. SystemVerilog ist eine Hardware-Beschreibungs-und Verifikationssprache (englisch Hardware Description and Verification Language, kurz HDVL genannt).Sie bietet Möglichkeiten zum Design und zur Verifikation von digitalen Schaltungen. These reside in a package, which I then include in my SystemVerilog module. How can we initialize a queue of structure with replication when non-replicated elements are also present? SystemVerilog typedef struct confusion I'm using Vivado 2017.1. And should we use TLS 1.3 as a guide? returns the number of items in the queue. Only packed data types and integer data types are allowed with in the packed struct. If Struct is not declared as rand, solver considers it as state variable. size() The size() method returns the number of items in the queue. The entire group can be referenced as a whole, or the individual data type can be referenced by name. The size of a queue is variable similar to a dynamic array, but a queue may be empty with no element and it is still a valid data structure.Queues can be used as LIFO (Last In … Tag: SystemVerilog queue design Queue Design in SystemVerilog: Entry is stored into the Queue in a certain order. Each element in the Queue is identified with a number, where 0 being the first element and $ being the last element. Bit-stream casting in systemVerilog:. Ask Question Asked 1 year, 8 months ago. I'm trying to use queues to populate data and use the data items in queue for comparison. SystemVerilog adds extended and new data types to Verilog for better encapsulation and compactness. I think this should solve the issue. How can internal reflection occur in a rainbow if the angle is less than the critical angle? The structured variables can be accessed using the variable name "my_data_struct". site design / logo © 2021 Stack Exchange Inc; user contributions licensed under cc by-sa. 4 comments on “ System Verilog : Queues ” Ramya October 27, 2014 at 7:05 pm. I have a packed struct defined as shown below typedef struct packed { logic bit1; logic [7:0] byte1; } MyPackedStruct; MyPackedStruct myPackedStruct; Is there any SV built in function that I could use to print the structures similar to above but having many more fields, without having to write my own method to print each of the fields using a in its definition. If you want to convert from one data type to another data type then you can use bitstream casting. assignment pattern. An example structure declaration is: Is there any example of multiple countries negotiating as a bloc for buying COVID-19 vaccines, except for EU? 07. The Entry could be taken out of queue (de-allocated) based on a certain protocol. Randomize Queue SystemVerilog In most of the queue use cases, queue is used as buffer or temporary storage. I tried out below ways without success. Example code on EDA Playground: https://www.edaplayground.com/x/3Qwh. For example if you want to sort a queue of integers in ascending order then you simply call the function sort (). In SystemVerilog is there a way to analyze a packed structure and determine it's overall size in bits? 5.2 Packed and unpacked arrays A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Initialize queue logic [7:0] q[$] = {1,2,3,4,5}; This works: localparam my_struct s = '{default:0, c:'1}; Thanks, Nachum. It has file extension .v or .vh: It has file extension .sv or .svh: 08. for example one structure type to another structure type, structure to int data type, structure to the array, structure to queue.If you want to represent a data type in a serial stream of bits. SystemVerilog Ming-Hwa Wang, Ph.D. COEN 207 SoC (System-on-Chip) Verification Department of Computer Engineering Santa Clara University Introduction SystemVerilog is a standard (IEEE std 1800-2005) unified hardware design, specification, and verification language, which provides a set of extensions to the IEEE 1364 Verilog HDL: Did "Antifa in Portland" issue an "anonymous tip" in Nov that John E. Sullivan be “locked out” of their circles because he is "agent provocateur"? push_front () inserts the given element at the front of the queue. SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. What is the simplest proof that the density of primes goes to zero? SystemVerilog queue of classes; Functional Verification Forums. That means, user doesn't want to do any class randomization on these struct fields. Packed array refers to dimensions declared after the type and before the data identifier Struct is defined with the Struct keyword followed by variables of multiple data type with in the curly braces. Modeling FIFO Communication Channels Using SystemVerilog Interfaces by Stuart Sutherland, Sutherland HDL, Inc. SNUG-Boston 2004 3 1-5 Verilog, SystemVerilog and SystemC XEach hardware design language has unique capabilities XThis paper is not about what language is best XThis paper is on how SystemVerilog enables modeling inter- SystemVerilog queue of classes. Working with SystemVerilog Structures by MBT A note on testing. Here all fields in basic structs have do-not-generate '!' SystemVerilog is not able to communicate directly with Python. The size of a queue is variable similar to a dynamic array, but a queue may be empty with no element and it is still a valid data structure. 2. Structure members can be any variable type, including user-defined types, and any constant type. typedef struct packed unsigned { logic [15:0] field_1; logic [7:0] field_2; UVM, Assertions, Functional Coverage, Object Oriented Programming & Random Testbenches Courses SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard.It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog. Section Objective: 3/4-day class includes introduction to SystemVerilog queues. SystemVerilog 4869. queue 18. ashishk. A "unit" in 'e' is equivalent [only static part] to "struct" in SV. how to, SystemVerilog The verification of digital circuits requires dealing with bits and bytes. in its definition. SystemVerilog is based on Verilog and some extensions, and since 2008 Verilog is now part of the same IEEE standard.It is commonly used in the semiconductor and electronic design industry as an evolution of Verilog. The new data types addition in SV ! SystemVerilog acts as a superset of Verilog with a lot extensions to Verilog … Typedef allows users to create their own names for type definitions that they will use frequently in their code. What is my registered address for UK car insurance? Instead, the SV code first needs to talk to a C code via a DPI-C, with the C code then able to talk to the Python code. Online Courses and Trainings in Systemverilog for RTL Design and SoC Verification. Some of these were created for designers but are also useful for testbenches. In this post of SystemVerilog Tutorial you will learn about the data structures most useful for verification. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. push_back() The push_back() method inserts the given element at the end of the queue. SystemVerilog Struct and Union – for Designers too. 18 posts. 09. Like as shown below: typedef struct {bit[31:0] addr, bit[3:0] id, bit[63:0] data; bit flag} packet_t; packet_t q1 [$]; I want to populate the addr everytime a new addr comes in, like: Or is there a way to achieve using unpacked array concatenation? A structure is declared using the struct keyword. concatenation operator {15 {'{a: A_VAL1, b: B_VAL1, default:0}}} delete () deletes the item at the specified index position. How can we initialize a queue of structure with replication when non-replicated elements are also present? SystemVerilog Introduction (8) SystemVerilog … Struct defined with the keyword Packed is referred as packed struct Structures and unions work much like they do in the C programming language. Each member may belong to different or same data type. EDIT: Another example, this time with a dynamic array or queue: bit [0:2] values[$]= '{3,5,6}; Queues can be used to model a last in, first out buffer or first in, first out buffer. Project settings should say SystemVerilog 2005; You should put the struct in a separate file, and then include it with all of the files that use the struct, e.g. If you are having problems with SystemVerilog constructs; write a small test that focuses just on the items you want to verify; otherwise other factors in your code may cause the things not to work and you may infer an erroneous conclusion. The simulator will take the set of values and pack them into one big bit vector. August 13, 2014 at 10:48 am. Like as shown below: typedef struct {bit[31:0] addr, bit[3:0] id, bit[63:0] data; bit flag} packet_t; packet_t q1 [$]; I want to populate the addr everytime a … It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. You can add an explicit type to an assignment pattern so it can be used in a self-determined context. SystemVerilog adds a new 2-state data types that can only have bits with 0 or 1 values unlike verilog 4-state data types which can have 0, 1, X and Z. SystemVerilog also allows user to define new data types. Scope: SystemVerilog is a Unified Hardware Design, Specification and Verification language that is based on the work done by Accellera, a consortium of Electronic Design Automation (EDA), semiconductor, and system companies. SystemVerilog is a combination of both Hardware Description Language (HDL) and Hardware Verification Language (HVL) and combined termed as HDVL. Here all fields in basic structs have do-not-generate '!' Queues In SystemVerilog:. A "unit" in 'e' is equivalent [only static part] to "struct" in SV. A structure is a convenient way of grouping several pieces of related information together. What's the word for someone who awkwardly defends/sides with/supports their bosses, in a vain attempt to get their favour? How to pass a SystemVerilog struct containing a dynamic array via DPI-C? A Queue is analogous to one dimensional array which grows and shrink … Introduction to Verification and SystemVerilog, SystemVerilog TestBench and Its components. SystemVerilog allows unpackedstructs to be declared as rand for randomization. Queues & Lists System Verilog 3.0 Interfaces Data Types & Enums Structures & Unions Advanced Operators Control Flow Casting Verilog2K Multi-D Arrays Generate Automatic Tasks Gate Level Modeling & Timing Verilog95 Hardware Concurrency SV3.0 Focus: enhance design language capabilities SV3.1 Focus: design language cleanup SystemVerilog. Also, the parallel programming of FPGA's comes easy to me. The SystemVerilog struct groups the data types of multiple types. It is similar to a one-dimensional unpacked array that grows and shrinks automatically. system stack hardware open-hardware priority-queue data-structures rtl verilog systemverilog fifo hdl system-verilog hardware-description-language Updated Apr 2, 2020; SystemVerilog ; Aya-Amin / Verilog-Projects Star 0 Code Issues Pull requests verilog computer-architecture system-verilog Updated Jul … push_front() The push_front() method inserts the given element at the front of the queue. January 17, 2017 April 28, 2017 by Jason Yu April 28, 2017 by Jason Yu Struct is defined with the Struct keyword followed by variables of multiple data type with in the curly braces. A "struct" in 'e' is equivalent to "class" [Dynamic] in SV. 10. Each element in the Queue is identified with a number, where 0 being the first element and $ being the last element. SystemVerilog queues cheatsheet. A queue type of array grows or shrinks to accommodate the number elements written to the array at runtime. The pop_back() method removes and returns the last element of the queue. SystemVerilog struct assignment You may have occasion to initialize a structure in SystemVerilog: typedef struct {int f1; int f2; int f3;} set_of_values_T; set_of_values_T set_of_values = {1, 2, -3}; This might seem fine, but the above assignment is actually a concatenation. By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy. Ip-ul dvs este: 40.77.167.65 Numele serverului este: cloud316.mxserver.ro Cauzele comunute de blocare sunt autentificarile gresite, in mod special parola, la WHM, cPanel, adresa de email sau FTP In the below example, variable of bit type are grouped in the struct. SystemVerilog uses the '{} construct to differentiate a list of values from a concatenation, {}. It supports Wire and Reg datatype. It is based on hierarchy of modules. Data Types. SystemVerilog queue of classes; Functional Verification Forums. SystemVerilog Struct and Union – for Designers too. This allows the reuse of classes with multiple interfaces. That means, user doesn't want to do any class randomization on these struct fields. my_struct s = '{default:'1, c:0}; is equivalent to my_struct s = '{a:16'hFFFF, b:16'hFFFF, c:16'h0000}; my_struct s = '{default:0, c:'1}; is equivalent to my_struct s = '{a:16'h0000, b:16'h0000, c:16'hFFFF}; Hi, I’m trying to use struct as data type in queues. systemverilog.io is a resource that explains concepts related to ASIC, FPGA and system design. What is the current school of thought concerning accuracy of numeric conversions of measurements? However assignment pattern can be assigned to unpacked structures. push_back () inserts the given element at the end of the queue. I have over 40 years programming experience, including over 25 years of object oriented programming experience. If you continue to use this site we will assume that you are happy with it. if you use Enhance Ability: Cat's Grace on a creature that rolls initiative, does that creature lose the better roll when the spell ends? To make this kind of code clear, the typedef facility was introduced. The struct uses three different types: byte, int (which are small values) and a packed 2-dimensional array. Elsewhere, I have instantiated a bank of registers that I wish to initialize to the appropriate value as defined in the above parameter. Assignment pattern is illegal due to: Replication field exceeds the insert () inserts the given item at the specified index position. struct {int a; byte b; bit [7:0] c;} my_data_struct; The keyword "struct" declares a structure to holds the details of four fields namely a,b and c. These are members of the structures. By default struct is of Unpacked type, i.e struct without Packed keyword. Use Exact Matching. Learn to use UVM environments, agents, sequencers, drivers, and monitors - Setting up the driver is a critical step. Here is a minimal working example of the problem: Below example compiles fine (using Cadence Incisive/Xcelium) if I comment out the import "DPI-C" statement and the call to print_object(s);. Home / Forums / SystemVerilog / Issue with sort() function of queue/array; Issue with sort() function of queue/array. i.e. System verilog packed array of structs. Feb-9-2014 : Example - struct : 1 `timescale 1ns/10ps 2 3 // Type define a struct, and put it outside module 4 // So that other modules can also use it 5 typedef struct { 6 byte a; 7 reg b; 8 shortint unsigned c; 9} myStruct; 10 11 module struct_data (); 12 13 // Define a local struct. ! And unions work much like they do in the queue ( HDL ) and combined termed as HDVL the items. To another data type system allows you to define quite complex types and! Notes and errors go away and Trainings in SystemVerilog, SystemVerilog TestBench and Its components of these created... Push_Front ( ) function of queue/array policy and cookie policy use TLS 1.3 a. Includes introduction to SystemVerilog queues create an IEEE standard that is leveraged from Accellera 3.1a. Is less than the critical angle awkwardly defends/sides with/supports their bosses, in a package, which I then in! To create their own names for type definitions that they will use frequently their. And paste this URL into your RSS reader of grouping several pieces of related information together this kind of clear! Unpacked type, including over 25 years of object oriented programming experience 6 types... Your coworkers to find and share information touching the ground behind you as you walk declared inside structs are supported! My SystemVerilog module called sort ( ) function of queue/array as a bloc for buying COVID-19 vaccines, except EU! The ' { default:0, C: ' 1 } ; Thanks, Nachum so it can be referenced a! `` my_data_struct '' kind of code clear, the communication will fail verifies the electronic circuits written in a Description! The push_back ( ) same data type system allows you to define quite types! Of values and pack them into one big bit vector queues ” Ramya October 27 2014! And returns the last element of the same data type can be either packed or.!, needs to follow certain guidelines, otherwise, the typedef facility was introduced Constructs ; interface OOPS. Article ’ s data type system allows you to define quite complex types Verilog: queues ” Ramya October,. Queues to populate data and use the data items in queue for.. Bank of registers that I wish to initialize to the array at runtime type_1..., where 0 being the first in, first out buffer or first a... 0 being the first in, first out buffer or first in, first out which... For RTL design and SoC Verification model a last in, first scheme. My_Data_Struct '' `` my_data_struct '' elements which can grow and shrink returns the number items! Take the set of values and pack them into one big bit vector into int. Or same data type in queues IEEE Std 1800-2012 § 10.9 assignment patterns wish to initialize to the appropriate as... ; Thanks, Nachum to subscribe to this RSS feed, copy and paste this into! To differentiate a list of values from a concatenation, { } construct to a. As rand for randomization learn, share knowledge, and any constant type frequently! Structure is a private, secure spot for you and your coworkers to find and share.! Ramya October 27, 2014 at 7:05 pm, variable of bit type are grouped in the curly.. The ground behind you as you walk edit, save, simulate synthesize. A resource that explains concepts related to ASIC, FPGA and system design ) deletes the item at the of! For reverse sorting there is a similar function called rsort ( ) inserts the item! Hvl ) and Hardware Verification Language ( HVL ) and combined termed as HDVL VHDL and c++ programming.! Logic [ 10-1:0 ] addr ; SystemVerilog struct and Union – for Designers.... Ieee Std 1800-2012 data structures most useful for Testbenches struct as data type system allows to! `` class '' [ Dynamic ] in SV ask Question Asked 1 year, 8 ago. Called sort ( ) the SystemVerilog struct groups the data types of types. Critical angle was introduced a `` struct '' in ' e ' is equivalent to `` ''. Structures and unions work much like they do in the below example, variable of bit type grouped...

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